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1 ds05-11025-2e fujitsu semiconductor data sheet memory cmos 4 4 m 4 bit synchronous dynamic ram mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l cmos 4-bank 4,194,304-word 4 bit synchronous dynamic random access memory n description the fujitsu mb81164442a is a cmos synchronous dynamic random access memory (sdram) containing 67,108,864 memory cells accessible in a 4-bit format. the mb81164442a features a fully synchronous operation referenced to a positive edge clock whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. the mb81164442a sdram is designed to reduce the complexity of using a standard dynamic ram (dram) which requires many control signal timing constraints, and may improve data bandwidth of memory as much as 5 times more than a standard dram. the mb81164442a is ideally suited for workstations, personal computers, laser printers, high resolution graphic adapters/accelerators and other applications where an extremely large memory and bandwidth are required and where a simple interface is needed. n product line & features parameter mb81164442a -125/-125l -100/-100l -84/-84l -67/-67l clock frequency 125 mhz max. 100 mhz max. 84 mhz max. 67 mhz max. burst mode cycle time 8 ns min. 10 ns min. 12 ns min. 15 ns min. ras access time 45 ns max. 54 ns max. 56 ns max. 60 ns max. cas access time 21 ns max. 24 ns max. 26 ns max. 30 ns max. access time from clock (cl = 3) 7.5 ns max. 8.5 ns max. 8.5 ns max. 9 ns max. operating current (2 banks active) 160 ma max. 140 ma max. 130 ma max. 120 ma max. power down mode current (i cc2p ) 3 ma max. (std power) 1 ma max. (low power) self refresh current (i cc6 ) 2 ma max. (std power) 500 m a max. (low power) single +3.3 v supply 0.3 v tolerance lvttl compatible i/o 4 k refresh cycles every 65.6 ms four bank operation burst read/write operation and burst read/single write operation capability standard and low power versions programmable burst type, burst length, and cas latency auto-and self-refresh (every 16 m s) cke power down mode output enable and input data mask
2 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n package package and ordering information 54-pin plastic (400 mil) tsop-ii, order as mb81164442a- fn (std power) and mb81164442a- lfn (low power) plastic tsop package (fpt-54p-m02) (normal bend) marking side
3 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n block diagram fig. 1 ? mb81164442a block diagram bank-1 v cc v ss /v ssq clk cke a 0 to a 11 , ap dq 0 to dq 3 command decoder clock buffer address buffer/ register i/o data buffer/ register mode register ras cas we dram core (4,096 1,024 4) col. addr. ras cas we cs bank-0 i/o row addr. to each block control signal latch dqm v ccq bank-2 bank-3 a 12 , a 13 column address counter
4 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n pin assignments and descriptions 54-pin tsop (top view) * : these pins are connected internally in the chip. pin number symbol function 1, 3, 9, 14, 27, 43, 49 v cc , v ccq supply voltage 5, 11, 44, 50 dq 0 to dq 3 data i/o 6, 12, 28, 41, 46, 52, 54 v ss , v ssq * ground 2, 4, 7, 8, 10, 13, 15, 36, 40, 42, 45, 47, 48, 51, 53 n.c. no connection 16 we write enable 17 cas column address strobe 18 ras row address strobe 19 cs chip select 20, 21 a 12 (ba 0 ), a 13 (ba 1 ) bank select (bank address) 22 ap auto precharge enable 22, 23, 24, 25, 26, 29, 30, 31, 32, 33, 34, 35 a 0 to a 11 address input row: a 0 to a 11 column: a 0 to a 9 37 cke clock enable 38 clk clock input 39 dqm input mask/output enable ras a 1 a 0 a 10 /ap a 13 cs cas we v ccq v ssq v ccq v ssq dq 1 dq 0 v cc a 6 a 7 a 8 a 9 cke clk dqm v ccq v ssq v ccq v ssq dq 2 dq 3 v ss v cc a 3 a 2 v ss a 4 a 5 (making side) 42 41 40 39 38 37 36 35 34 54 53 52 51 50 49 48 47 46 45 1 2 3 4 5 9 10 6 7 8 13 14 15 16 17 18 19 20 21 22 44 43 11 12 33 32 31 30 29 28 23 24 25 26 27 n.c. n.c. n.c. n.c. n.c. n.c. n.c. a 12 v cc n.c. n.c. n.c. n.c. n.c. n.c. v ss n.c. n.c. a 11
5 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n functional truth table note 1 command truth table notes 2, 3, and 4 notes: *1. v = valid, l = logic low, h = logic high, x = either l or h. *2. all commands assumes no csus command on previous rising edge of clock. *3. all commands are assumed to be valid state transitions. *4. all inputs are latched on the rising edge of clock. *5. nop and desl commands have the same effect on the part. *6. read, reada, writ and writa commands should only be issued after the corresponding bank has been activated (actv command). refer to state diagram. *7. actv command should only be issued after corresponding bank has been precharged (pre or pall command). *8. required after power up. *9. mrs command should only be issued after all banks have been precharged (pre or pall command) and dq has been in hi-z. refer to state diagram. function notes symbol cke cs ras cas we a 13 , a 12 (ba) a 10 (ap) a 11 a 9 to a 0 n-1 n device deselect *5 desl h x h x x x xxxx no operation *5 nop h x l h h h xxxx burst stop bst h x l h h l xxxx read *6 read h x l h l h v l x v read with auto-precharge *6 reada h x l h l h v h x v write *6 writ h x l h l l v l x v write with auto-precharge *6 writa h x l h l l v h x v bank active (ras ) *7 actv h x l l h h vvvv precharge single bank pre h x l l h l v l x x precharge all banks pall h x l l h l x h x x mode register set *8, 9 mrs h x l l l l l l l v
6 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l dqm truth table cke truth table notes: *1. the csus command requires that at least one bank is active. refer to state diagram. *2. ref and self commands should only be issued after all banks have been precharged (pre or pall command). refer to state diagram. *3. self and pd commands should only be issued after the last read data have been appeared on dq. *4. cke should be held high within t rc . function command cke dqm n-1 n data write/output enable enbl h x l data mask/output disable mask h x h current state function notes symbol cke cs ras cas we a 13 , a 12 (ba) a 10 (ap) a 11 , a 9-0 n-1 n bank active clock suspend mode entry *1 csus h l xxxxxxx any (except idle) clock suspend continue *1 l l xxxxxxx clock suspend clock suspend mode exit l h xxxxxxx idle auto-refresh command *2 ref h h l l l h x x x idle self-refresh entry *2, 3 self h l l l l h x x x self refresh self-refresh exit *4 selfx lhlhhhxxx lhhxxxxxx idle power down entry *2, 3 pd hllhhhxxx hlhxxxxxx power down power down exit lhlhhhxxx lhhxxxxxx
7 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l operation command table (applicable to single bank) (continued) current state cs ras cas we addr command function notes idle h x x x x desl nop l h h h x nop nop l h h l x bst nop lhlh ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv bank active l l h l ba, ap pre/pall nop (pall may affect other banks.) l l l h x ref/self auto-refresh or self-refresh *3 llll mode mrs mode register set (idle after i mrd ) *3, 7 bank active h x x x x desl nop l h h h x nop nop l h h l x bst nop lhlh ba, ca, ap read/reada begin read; determine ap l h l l ba, ca, ap writ/writa begin write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall precharge; determine precharge type (pall may affect other banks.) l l l h x ref/self illegal llll mode mrs illegal
8 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l (continued) current state cs ras cas we addr command function notes read h x x x x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end ? bank active) l h h l x bst burst stop ? bank active lhlh ba, ca, ap read/reada terminate burst, new read; determine ap l h l l ba, ca, ap writ/writa terminate burst, start write; determine ap *4 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge ? idle; determine precharge type l l l h x ref/self illegal llll mode mrs illegal write h x x x x desl nop (continue burst to end ? bank active) lhhh x nop nop (continue burst to end ? bank active) l h h l x bst burst stop ? bank active lhlh ba, ca, ap read/reada terminate burst, start read; determine ap l h l l ba, ca, ap writ/writa terminate burst, new write; determine ap l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall terminate burst, precharge ? idle; determine precharge type (pall may affect other banks.) *4 l l l h x ref/self illegal llll mode mrs illegal
9 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l (continued) current state cs ras cas we addr command function notes read with auto- precharge h x x x x desl nop (continue burst to end ? precharge ? idle) lhhh x nop nop (continue burst to end ? precharge ? idle) l h h l x bst illegal lhlh ba, ca, ap read/reada illegal l h l l ba, ca, ap writ/writa illegal l l h h ba, ra actv illegal *2 l l h l ba pre illegal *2 l l h l ap pall illegal l l l h x ref/self illegal llll mode mrs illegal write with auto- precharge h x x x x desl nop (continue burst to end ? precharge ? idle) lhhh x nop nop (continue burst to end ? precharge ? idle) l h h l x bst illegal lhlh ba, ca, ap read/reada illegal l h l l ba, ca, ap writ/writa illegal l l h h ba, ra actv illegal *2 l l h l ba pre illegal *2 l l h l ap pall illegal l l l h x ref/self illegal llll mode mrs illegal
10 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l (continued) current state cs ras cas we addr command function notes precharge h x x x x desl nop (idle after t rp ) l h h h x nop nop (idle after t rp ) l h h l x bst nop (idle after t rp ) lhlh ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba, ap pre/pall nop (pall may affect other bank) *5 l l l h x ref/self illegal llll mode mrs illegal bank activating h x x x x desl nop (bank active after t rcd ) l h h h x nop nop (bank active after t rcd ) l h h l x bst nop (bank active after t rcd ) lhlh ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2, 8 l l h l ba pre illegal *2 l l h l ap pall illegal l l l h x ref/self illegal llll mode mrs illegal
11 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l (continued) current state cs ras cas we addr command function notes write recovering h x x x x desl nop (bank active after t wr ) l h h h x nop nop (bank active after t wr ) l h h l x bst nop (bank active after t wr ) lhlh ba, ca, ap read/reada start read; determine ap *4 l h l l ba, ca, ap writ/writa new write; determine ap l l h h ba, ra actv illegal *2 l l h l ba pre illegal *2 l l h l ap pall illegal l l l h x ref/self illegal llll mode mrs illegal write recovering with auto- precharge h x x x x desl nop (precharge after i rwl ) l h h h x nop nop (precharge after i rwl ) l h h l x bst illegal lhlh ba, ca, ap read/reada illegal *2 l h l l ba, ca, ap writ/writa illegal *2 l l h h ba, ra actv illegal *2 l l h l ba pre illegal *2 l l h l ap pall illegal l l l h x ref/self illegal llll mode mrs illegal
12 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l (continued) abbreviations: ra = row address ba = bank address ca = column address ap = auto precharge current state cs ras cas we addr command function notes refreshing h x x x x desl nop (idle after t rc ) l h h x x nop/bst nop (idle after t rc ) lhlx x read/reada/ writ/writa illegal llhx x actv/ pre/pall illegal lllx x ref/self/ mrs illegal mode register setting h x x x x desl nop (idle after i mrd ) l h h h x nop nop (idle after i mrd ) l h h l x bst illegal lhlx x read/reada/ writ/writa illegal llxx x actv/pre/ pall/ref/ self/mrs illegal
13 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l command truth table for cke (continued) current state cke n-1 cke n cs ras cas we addr function notes self- refresh hxxxxx x inv alid lhhxxx x exit self-refresh (self-refresh recovery ? idle after t rc ) lhlhhh x exit self-refresh (self-refresh recovery ? idle after t rc ) lhlhhl x illegal lhlhlx x illegal l h l l x x x illegal l lxxxx x nop (maintain self-refresh) self- refresh recovery lxxxxx x inv alid h h h x x x x idel after t rc h h l h h h x idel after t rc h h l h h l x illegal hhlhlx x illegal h h l l x x x illegal hlxxxx x illegal
14 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l (continued) current state cke n-1 cke n cs ras cas we addr function notes power down hxxxxx x inv alid lh hxxx x exit power down mode ? idle lhhh x l lxxxx x nop (maintain power down mode) l h l l x x x illegal lhlhlx x illegal lhlhhl x illegal all banks idle h h h x x x refer to the operation command table. h h l h x x refer to the operation command table. h h l l h x refer to the operation command table. h h l l l h x auto-refresh hhllll mode refer to the operation command table. h l h x x x x power down *6 h l l h h h x power down *6 h l l h h l illegal h l l h l x x illegal h l l l h x x illegal hllllh x self-refresh *6 hlllll x illegal lxxxxx x inv alid
15 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l (continued) notes: *1. all entries assume the cke was high during the proceeding clock cycle and the current clock cycle. *2. illegal to bank in speci?d state; entry may be legal in the bank speci?d by ba, depending on the state of that bank. *3. illegal if any bank is not idle. *4. must satisfy bus contention, bus turn around, and/or write recovery requirements. *5. nop to bank precharging or in idle state. may precharge bank spesi?d by ba (and ap). *6. self command should only be issued after the last read data have been appeared on dq. *7. mrs command should only be issued on condition that all dq are in hi-z. *8. t rrd must be satis?d for other banks. current state cke n-1 cke n cs ras cas we addr function notes bank active bank activating read/write write recovering hhxxxx x refer to the operation command table. hlxxxx x begin clock suspend next cycle lhxxxx x exit clock suspend next cycle l lxxxx x maintain clock suspend clock suspend hxxxxx x inv alid lhxxxx x exit clock suspend next cycle l lxxxx x maintain clock suspend any state other than listed above lxxxxx x inv alid hhxxxx x refer to the operation command table. hlxxxx x illegal
16 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n functional description sdram basic function three major differences between this sdram and conventional drams are: synchronized operation, burst mode, and mode register. the synchronized operation is the fundamental difference. an sdram uses a clock input for the synchronization, where the dram is basically asynchronous memory although it has been using two clocks, ras and cas . each operation of dram is determined by their timing phase differences while each operation of sdram is determined by commands and all operations are referenced to a positive clock edge. fig 3 shows the basic timing diagram differences between sdrams and drams. the burst mode is a very high speed access mode utilizing an internal column address generator. once a column addresses for the ?st access is set, following addresses are automatically generated by the internal column address counter. the mode registe r is to justify the sdram operation and function into desired system conditions. mode register table shows how sdram can be con?ured for system requirement by mode register programming. clock (clk) and clock enable (cke) all input and output signals of sdram use register type buffers. a clk is used as a trigger for the register and internal burst counter increment. all inputs are latched by a positive edge of clk. all outputs are validated by the clk. cke is a high active clock enable signal. when cke = low is latched at a clock input during active cycle, the next clock will be internally masked. during idle state (all banks have been precharged), the power down mode (standby) is entered with cke = low and this will make extremely low standby current. chip select (cs ) cs enables all commands inputs, ras , cas , and we , and address input. when cs is high, command signals are negated but internal operation such as burst cycle will not be suspended. if such a control isn? needed, cs can be tied to ground level. command input (ras , cas and we ) unlike a conventional dram, ras , cas , and we do not directly imply sdram operation, such as row address strobe by ras . instead, each combination of ras , cas , and we input in conjunction with cs input at a rising edge of the clk determines sdram operation. refer to functional truth table in page 5. address input (a 0 to a 11 ) address input selects an arbitrary location of a total of 4,194,304 words of each memory cell matrix. a total of fourteen address input signals are required to decode such a matrix. sdram adopts an address multiplexer in order to reduce the pin count of the address line. at a bank active command (actv), twelve row addresses are initially latched and the remainder of ten column addresses are then latched by a column address strobe command of either a read command (read or reada) or write command (writ or writa). bank select (a 13 , a 12 ) this sdram has four banks and each bank is organized as 4 m words by 4-bit. bank selection by a 13 , a 12 occurs at bank active command (actv) followed by read (read or reada), write (writ or writa), and precharge command (pre).
17 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l data input and output (dq 0 to dq 3 ) input data is latched and written into the memory at the clock following the write command input. data output is obtained by the following conditions followed by a read command input: t rac ; from the bank active command when t rcd (min) is satis?d. (this parameter is reference only.) t cac ; from the read command when t rcd is greater than t rcd (min). t ac ; from the clock edge after t rac and t cac . the polarity of the output data is identical to that of the input. data is valid between access time (determined by the three conditions above) and the next positive clock edge (t oh ). data i/o mask (dqm) dqm is an active high enable input and has an output disable and input mask function. during burst cycle and when dqm = high is latched by a clock, input is masked at the same clock and output will be masked at the second clock later while internal burst counter will increment by one or will go to the next stage depending on burst type. burst mode operation and burst type the burst mode provides faster memory access. the burst mode is implemented by keeping the same row address and by automatic strobing column address. access time and cycle time of burst mode is speci?d as t ac and t ck , respectively. the internal column address counter operation is determined by a mode register which de?es burst type and burst count length of 1, 2, 4 or 8 bits of boundary. in order to terminate or to move from the current burst mode to the next stage while the remaining burst count is more than 1, the following combinations will be required: the burst type can be selected either sequential or interleave mode if burst length is 2, 4 or 8. the sequential mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least signi?ant address (= 0). the interleave mode is a scrambled decoding scheme for a 0 and a 2 . if the ?st access of column address is even (0), the next address will be odd (1), or vice-versa. current stage next stage method (assert the following command) burst read burst read read command burst read burst write 1st step mask command (normally 3 clock cycles) 2nd step write command after l owd burst write burst write write command burst write burst read read command burst read precharge precharge command burst write precharge precharge command
18 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l when the full burst operation is executed at single write mode, auto-precharge command is valid only at write operation. the burst type can be selected either sequential or interleave mode. but only the sequential mode is usable to the full column burst. the sequential mode is an incremental decoding scheme within a boundary address to be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary address and then wraps round to least signi?ant address (= 0). full column burst and burst stop command (bst) the full column burst is an option of burst length and available only at sequential mode of burst type. this full column burst mode is repeatedly access to the same column. if burst mode reaches end of column address, then it wraps round to ?st column address (= 0) and continues to count until interrupted by the news read (read) /write (writ), precharge (pre), or burst stop (bst) command. the selection of auto-precharge option is illegal during the full column burst operation except write command at burst read & single write mode. the bst command is applicable to terminate the burst operation. if the bst command is asserted during the burst mode, its operation is terminated immediately and the internal state moves to bank active. when read mode is interrupted by bst command, the output will be in high-z. for the detail rule, please refer to timing diagram-8. when write mode is interrupted by bst command, the data to be applied at the same time with bst command will be ignored. burst read & single write the burst read and single write mode provides single word write operation regardless of its burst length. in this mode, burst read operation does not be affected by this mode. burst length starting column address a 2 a 1 a 0 sequential mode interleave 2 x x 0 0 ?1 0 ?1 x x 1 1 ?0 1 ?0 4 x 0 0 0 ?1 ?2 ?3 0 ?1 ?2 ? 3 x 0 1 1 ?2 ?3 ?0 1 ?0 ?3 ?2 x 1 0 2 ?3 ?0 ?1 2 ?3 ?0 ?1 x 1 1 3 ?0 ?1 ?2 3 ?2 ?1 ?0 8 0 0 0 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 0 0 1 1 ?2 ?3 ?4 ?5 ?6 ?7 ?0 1 ?0 ?3 ?2 ?5 ?4 ?7 ?6 0 1 0 2 ?3 ?4 ?5 ?6 ?7 ?0 ?1 2 ?3 ?0 ?1 ?6 ?7 ?4 ?5 0 1 1 3 ?4 ?5 ?6 ?7 ?0 ?1 ?2 3 ?2 ?1 ?0 ?7 ?6 ?5 ?4 1 0 0 4 ?5 ?6 ?7 ?0 ?1 ?2 ?3 4 ?5 ?6 ?7 ?0 ?1 ?2 ?3 1 0 1 5 ?6 ?7 ?0 ?1 ?2 ?3 ?4 5 ?4 ?7 ?6 ?1 ?0 ?3 ?2 1 1 0 6 ?7 ?0 ?1 ?2 ?3 ?4 ?5 6 ?7 ?4 ?5 ?2 ?3 ?0 ?1 1 1 1 7 ?0 ?1 ?2 ?3 ?4 ?5 ?6 7 ?6 ?5 ?4 ?3 ?2 ?1 ?0
19 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l precharge and precharge option (pre, pall) sdram memory core is the same as conventional drams? requiring precharge and refresh operations. precharge rewrites the bit line and to reset the internal row address line and is executed by the precharge command (pre). with the precharge command, sdram will automatically be in standby state after precharge time (t rp ). the precharged bank is selected by combination of ap and a 13 , a 12 when precharge command is asserted. if ap = high, all banks are precharged regardless of a 13 , a 12 (pall). if ap = low, a bank to be selected by a 13 , a 12 is precharged (pre). the auto-precharge enters precharge mode at the end of burst mode of read or write without precharge command assertion. this auto precharge is entered by ap = high when a read or write command is asserted. refer to functional truth table. auto-refresh (ref) auto-refresh uses the internal refresh address counter. the sdram auto-refresh command (ref) generates precharge command internally. all banks of sdram should be precharged prior to the auto-refresh command. the auto-refresh command should also be asserted every 16 m s or a total 4096 refresh commands within a 65.6 ms period. self-refresh entry (self) self-refresh function provides automatic refresh by an internal timer as well as auto-refresh and will continue the refresh function until cancelled by selfx. the self-refresh is entered by applying an auto-refresh command in conjunction with cke = low (self). once sdram enters the self-refresh mode, all inputs except for cke will be ?on? care (either logic high or low level state) and outputs will be in a high-z state. during a self-refresh mode, cke = low should be maintained. self command should only be issued after last read data has been appeared on dq. note: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted prior to the self-refresh mode entry. self-refresh exit (selfx) to exit self-refresh mode, apply minimum t pde after cke brought high, and then the nop command (nop) or the deselect command (desl) should be asserted within one t rc period. cke should be held high within one t rc period after t pde . refer to timing diagram for the detail. it is recommended to assert an auto-refresh command just after the t rc period to avoid the violation of refresh period. note: when the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted after the self-refresh exit. mode register set (mrs) the mode register of sdram provides a variety of different operations. the register consists of four operation ?lds; burst length, burst type, cas latency, and operation code. refer to mode register table in page 34. the mode register can be programmed by the mode register set command (mrs). each ?ld is set by the address line. once a mode register is programmed, the contents of the register will be held until re-programmed by another mrs command (or part loses power). mrs command should only be issued on condition that all dq is in hi-z. the condition of the mode register is unde?ed after the power-up stage. it is required to set each ?ld after initialization of sdram. refer to power-up initialization below.
20 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l power-up initialization the sdram internal condition after power-up will be unde?ed. it is required to follow the following power on sequence to execute read or write operation. 1. apply power and start clock. attempt to maintain either nop or desl command at the input. 2. maintain stable power, stable clock, and nop condition for a minimum of 200 m s. 3. precharge all banks by precharge (pre) or precharge all command (pall). 4. assert minimum of 8 auto-refresh command (ref). 5. program the mode register by mode register set command (mrs). in addition, it is recommended dqm and cke to track v cc to insure that output is high-z state. the mode register set command (mrs) can be set before 8 auto-refresh command (ref).
21 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l cas latency = 1 ras cas dq clk cs dq t si ras cas cke we burst length = 4 active read/write precharge address hh h t hi h : read l : write ba * ra ba * ca ba * ap (a 10 ) row adress select column address select precharge fig. 2 ? basic timing for conventional dram vs synchronous dynamic ram * : ba = ba 0 (a 12 ) and ba 1 (a 13 )
22 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l minimum clock latency or delay time for 1 bank operation notes: *1. assume no i/o con?ct. *2. if t rp t ck , minimum latency is a sum of bl + cl. *3. assume output is in high-z state. illegal command second command (same bank) first command mrs l mrd l mrd l mrd l mrd actv t rcd t rcd t rcd t rcd t ras t ras read 11 *1 1 *1 111 reada *2 bl + t rp *2 bl + t rp *2 bl + t rp *2 bl + t rp writ t wr t wr 11i rwl i rwl writa bl + t rp bl + t rp bl + t rp bl + t rp pre *3 t rp *3 t rp *3 t rp *3 t rp pall *3 t rp *3 t rp *3 t rp *3 t rp ref t rc t rc t rc t rc selfx t rc t rc t rc t rc mrs actv read reada writ writa pre pall ref self
23 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l minimum clock latency or delay time for 4 bank operation notes: *1. assume opposite bank is in idle state. *2. assume opposite bank is in active state. *3. assume no i/o con?ct. *4. if t rp t ck , minimum latency is a sum of bl + cl. *5. assume pall command dose not affect any operation on opposite bank. *6. assume output is in high-z sate. *7. assume an opposite bank is active and t ras is satis?d. illegal command second command (other bank) first command mrs l mrd l mrd l mrd l mrd actv *1 t rrd *2 1 *2 1 *2 1 *2 1 *7 1 *2 t ras read *1 1 *2 1 *2 1 *2 *3 1 *2 *3 1 *7 1 *2 t ras reada *1 1 1 *1 *4 bl + t rp *1 *4 bl + t rp writ *1 1 *2 1 *2 1 *2 1 *2 1 *7 1 *2 t ras writa *1 1 1 *1 bl + t rp *1 bl + t rp pre *1 t rp *1 1 *2 1 *2 1 *2 1 *2 11 *2 t ras *1 t rp *1 t rp *5 pall t rp t rp 11 *1 *6 t rp *1 *6 t rp ref t rc t rc t rc t rc selfx t rc t rc t rc t rc mrs actv read reada writ writa pre pall ref self
24 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l mode register set self refresh idle read suspend bank active auto refresh power down bank active suspend fig. 3 ? state diagram (simpli?d state diagram) write write suspend power on precharge read write with auto precharge read with auto precharge writ read read writ bst bst mrs self selfx ref actv cke cke\ cke cke\ cke read writ reada writa reada cke\ cke writa pre or pall pre or pall power applied definition of allows manual input automatic sequence writa reada pre or pall pre or pall cke\(pd)
25 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n absolute maximum ratings (see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions (referenced to v ss ) notes: *1. overshoot limit: v ih (max) = tbd. *2. undershoot limit: v il (min) = ?.5 v with a pulsewidth 5 ns. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the device? electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. n capacitance (t a = 25 c, f = 1 mhz) parameter symbol value unit voltage of v cc supply relative to v ss v cc , v ccq ?.5 to +4.6 v voltage at any pin relative to v ss v in , v out ?.5 to +4.6 v short circuit output current i out ?0 to +50 ma power dissipation p d 1.0 w storage temperature t stg ?5 to +125 c parameter notes symbol min. typ. max. unit supply voltage v cc , v ccq 3.0 3.3 3.6 v v ss , v ssq 000v input high voltage *1 v ih 2.0 v cc + 0.5 v input low voltage *2 v il ?.5 0.8 v ambient temperature t a 070 c parameter symbol typ. max. unit input capacitance, address c in1 ?pf input capacitance, except for address c in2 ?pf i/o capacitance c i/o ?pf
26 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n dc characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2 (continued) parameter symbol condition value unit min. max. output high voltage v oh(dc) i oh = ? ma 2.4 v output low voltage v ol(dc) i ol = 2 ma 0.4 v input leakage current (any input) i li 0 v v in v cc ; all other pins not under test = 0 v ?0 10 m a output leakage current i lo 0 v v in v cc ; data out disabled ?0 10 m a operating current (average power supply current) mb81164442a-125/l i cc1s no burst; t ck = min t rc = min one bank active 0 v v in v cc 90 ma mb81164442a-100/l 80 MB81164442A-84/l 75 mb81164442a-67/l 70 mb81164442a-125/l i cc1d no burst; t ck = min t rc = min 2 banks active 0 v v in v cc 160 ma mb81164442a-100/l 140 MB81164442A-84/l 130 mb81164442a-67/l 120 precharge standby current (power supply current) std power i cc2p cke = v il all banks idle t ck = min power down mode 0 v v in v cc ? ma low power 1 std power i cc2ps cke = v il all banks idle t ck = 0 v v in v cc ? ma low power 0.5 i cc2n cke = v ih all banks idle t ck = min 0 v v in v cc ?0ma i cc2ns cke = v ih t ck = input signal are stable. ?ma
27 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l (continued) parameter symbol condition value unit min. max. active standby current (power supply current) std power i cc3p cke = v il any bank active t ck = min 0 v v in v cc ? ma low power 3 std power i cc3ps cke = v il t ck = input signal are stable. ? ma low power 2 i cc3n cke = v ih any bank active t ck = min 0 v v in v cc ?5ma i cc3ns cke = v ih t ck = input signal are stable. ?0ma burst mode current (average power supply current) mb81164442a-125/l i cc4 t ck = min 0 v v in v cc 180 ma mb81164442a-100/l 150 MB81164442A-84/l 130 mb81164442a-67/l 100 refresh current #1 (average power supply current) mb81164442a-125/l i cc5 auto-refresh; t ck = min t rc = min 0 v v in v cc 205 ma mb81164442a-100/l 180 MB81164442A-84/l 165 mb81164442a-67/l 150 refresh current #2 (average power supply current) std power i cc6 self-refresh; cke = v il 0 v v in v cc 2 ma low power 0.5
28 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n ac characteristics (at recommended operating conditions unless otherwise noted.) note 2, 3, 4 parameter notes symbol mb81164442a -125/-125l mb81164442a -100/-100l mb81164442a -84/-84l mb81164442a -67/-67l unit min. max. min. max. min. max. min. max. clock period cl = 2 t ck 12 15 17 20 ns cl = 3 8 10 12 15 ns clock high time t ch 3.53.5??ns clock low time t cl 3.53.5??ns input set up time t si 2.5???ns input hold time t hi 1???ns access time from clock (t ck = min) *5, 6 cl = 2 t ac 9 9 10 ns cl = 3 7.5 8.5 8.5 ns output in low-z *7 t lz 2???ns output in high-z *7 cl = 2 t hz 2 9 3 9 3 10 3 10 ns cl = 3 7.5 8.5 8.5 9 ns output hold time *7 t oh 2???ns time between refresh t ref 65.6 65.6 65.6 65.6 ms transition time t t 0.5 2 0.5 2 0.5 2 0.5 2 ns power down exit time t pde 3???ns 10 9
29 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l base values for clock count/latency clock count formula note 13 parameter notes symbol mb81164442a -125/-125l mb81164442a -100/-100l mb81164442a -84/-84l mb81164442a -67/-67l unit min. max. min. max. min. max. min. max. ras cycle time *8 t rc 77 90 100 110 ns ras access time *9 t rac ?5?4?6?0ns cas access time *10,13 t cac ?1?4?6?0ns ras precharge time t rp 29?0?5?0ns ras active time t ras 48 100000 60 100000 65 100000 70 100000 ns ras to cas delay time *11 t rcd 24?0?0?0ns write recovery time t wr 8 10?2?5ns ras to ras bank active delay time t rrd 16?0?0?0ns write to precharge read delay time t rwl 8 10?2?5ns clock 3 (round off a whole number) base value clock period
30 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l latency - fixed values (the latency values on these parameters are ?ed regardless of clock period.) notes: *1. i cc depends on the output termination or load conditions, clock cycle rate, signal clocking rate and address change; the speci?d values are obtained with the output open and no termination register and one time address change. *2. an initial pause (desl or nop) of 200 m s is required after power-up followed by a minimum of eight auto-refresh cycles. *3. ac characteristics assume t t = 1 ns and 50 pf of capacitive load. *4. 1.4 v is the reference level for measuring timing of input signals. transition times are measured between v ih (min) and v il (max). (see fig. 5) *5. maximum value of cl = 2 depends on t ck . *6. t ac also speci?s the access time at burst mode except for ?st access. *7. speci?d where output buffer is no longer driven. t oh , t lz , and t hz de?e the times at which the output level achieves 200 mv. *8. actual clock count of t rc (l rc ) will be sum of clock count of t ras (l ras ) and t rp (l rp ). *9. t rac is a reference value. maximum value is obtained from the sum of t rcd (min) and t cac (max). *10. t cac is a reference value. *11. operation within the t rcd (min) ensures that t rac can be met; if t rcd is greater than the speci?d t rcd (min), access time is determined by t cac or t ac . *12. all base values are measured from the clock edge at the command input to the clock edge for the next command input. all clock counts are calculated by a simple formula: clock count equals base value divided by clock period (round off to a whole number). *13. the t cac depends on the cas latency. parameter notes symbol mb81164442a -125/-125l mb81164442a -100/-100l mb81164442a -84/-84l mb81164442a -67/-67l unit cke to clock disable l cke 1111 cycle dqm to output in high-z l dqz 2222 cycle dqm to input data delay l dqd 0000 cycle last output to write command delay l owd 2222 cycle write command to input data delay l dwd 0000 cycle precharge to output in high-z delay cl = 2 l roh 2222 cycle cl = 3 3333 cycle burst stop command to output in high-z delay cl = 2 l bsh 2222 cycle cl = 3 3333 cycle mode register access to banks active l mrd 2222 cycle cas to cas delay (min) l ccd 1111 cycle cas bank delay (min) l cbd 1111 cycle write to precharge read delay cl = 2 l rwl 1111 cycle cl = 3 1111 cycle
31 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l output note: ac characteristics are measured in this condition. this load circuits are not applicable for v oh and v ol . fig. 4 ? example of ac test load circuit r 1 = 50 w cl = 50 pf lvttl 1.4 v
32 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l t si t hi t ch t ck t ac t hz t oh t lz t cl clk input (control, addr. & data) output 2.0 v 1.4 v 0.8 v 1.4 v 2.0 v 0.8 v 1.4 v 2.4 v 0.4 v note: reference level of input signal is 1.4 v for lvttl. access time is measured at 1.4 v for lvttl. fig. 5 ? timing diagram, setup, hold and delay time clk cke t pde (min) nop don? care don? care command 1 clock (min) nop actv fig. 6 ? timing diagram, delay time for power down exit
33 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l fig. 7 ? timing diagram, pulse width t pde , t rp , t ras , t rcd , t rwl , t rrd command command clk input (control) note: this parameter is a limit value of the rising edge of the clock from one command input to next input. t pde is the latency value from the rising edge of cke. measurement reference voltage is 1.4 v. fig. 8 ? timing diagram, access time t rac t cac t ac clk ras cas dq (output) t rcd q (valid) (cas latency ?) t ck note: t rac and t cac are reference values. data can be obtained after t ac is satis?d.
34 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n mode register table a 2 a 1 a 0 burst length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 2 4 8 reserved reserved reserved full column 0 1 0 1 0 1 0 1 reserved 2 4 8 reserved reserved reserved reserved bt = 0 bt = 1 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 address op- code 0 0 cl bt bl mode register a 3 burst type sequential (wrap round, binary-up) interleave (wrap round, binary-up) 0 1 a 6 a 5 a 4 cas latency 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 mode register set a 9 op-code burst read & burst write burst read & single write 0 1 reserved reserved 2 3 reserved reserved reserved reserved notes: 1. when a 9 = 1, burst length at write is always one regardless of bl value. 2. bl = 1 and full column are not applicable to the interleave mode. a 1 a 0 00 a 13 a 12 00
35 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?1 : clock enable - read and write suspend (@ bl = 4) q1 q2 (no change) q3 (no change) q4 d1 not written d2 not written d3 d4 clk cke clk (internal) dq (read) dq (write) notes: 1. the latency of cke (l cke ) is one clock. 2. during read mode, burst counter will not be incremented/decremented at the next clock of csus command. output remain the same data. 3. during the write mode, data at the next clock of csus command is ignored. 1 33 1 22 22 i cke (1 clock) i cke (1 clock) timing diagram ?2 : clock enable - power down entry and exit nop pd(nop) don? care nop actv clk cke command 1 clock (min) 1 23 nop 3 notes: 1. precharge command (pre or pall) should be asserted if any bank is active and in the burst mode. 2. precharge command can be posted in conjunction with cke after the last read data have been appeared on dq. 3. the actv command can be latched after t pde (min) + 1 clock (min). it is recommended to apply nop command in conjunction with cke. it is also recommended to apply minimum of 4 clocks to stabilize external clock prior to actv command. t pde t ref (max)
36 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?3 : column address to column address input delay clk ras cas row address column address address i ccd (1 clock) t rcd (min) note: cas to cas address delay can be one or more clock period. i ccd i ccd i ccd column address column address column address column address timing diagram ?4 : different bank address input delay t rcd (min) t rrd (min) clk ras cas row address address bank 0 bank 1 bank 1 bank 1 bank 0 bank 0 ba t rcd (min) i cbd i cbd column address row address column address column address column address
37 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?5 : dqm - input mask and output disable (@ bl = 4) clk dqm (@ read) dq (@ read) dqm (@ write) dq (@ write) q1 q2 hi-z q4 end of burst d1 masked d3 d4 end of burst i dqz (2 clocks) i dqd (same clock) timing diagram ?6 : precharge timing (applied to the same bank) t ras (min) clk command actv precharge
38 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?7 : read interrupted by precharge (example @ cl = 2, bl = 4) clk command dq command dq command dq command dq hi-z q1 precharge q1 q2 q1 q2 q3 q1 q2 q3 q4 hi-z hi-z no effect (end of burst) note: in case of cl = 2, the l roh is 2 clock. in case of cl = 3, the l roh is 3 clock. i roh (2 clocks) i roh (2 clocks) i roh (2 clocks) precharge precharge precharge
39 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?8 : read interrupted by burst stop (example @ bl = 8) clk command (cl = 2) dq command (cl = 3) dq q n q n+1 hi-z hi-z q n+2 q n-1 q n-2 q n q n+1 q n? q n? l bsh (2 clocks) l bsh (3 clocks) bst bst notes: 1. in a case of cl = 2 and bl = 8, ? should be 1 n 6. when ? is 7 n 8, the bst command takes no effect. in a case of cl = 3 and bl = 8, ? should be 1 n 5. when ? is 6 n 8, the bst command takes no effect. 2. the bst command is valid for all burst lengthes (1, 2, 4, 8 and full column). timing diagram ?9 : write interrupted by burst stop (example @ bl = 2) clk command dq last data-in masked by bst bst command
40 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?10 : write interrupted by precharge (example @ cl = 3) t rp (min) t rwl (min) clk command dq active data-in last data-in masked by pre note: the precharge command (pre) should only be issued after the t rwl of ?al data input, is satis?d. precharge timing diagram ?11 : read interrupted by write (example @ cl = 3, bl = 4) clk command dqm dq data out masked data i n data i n note 1 note 2 note 3 write notes: 1. first dqm makes high-impedance state high-z between last output and ?st input data. 2. second dqm makes internal output data mask to avoid bus contention. 3. third dqm in illustrated above also makes internal output data mask. if burst read ends (?al data output) at or after the second clock of burst write, this third dqm is required to avoid internal bus contention. i dwd (same clock) i owd (2 clocks) i dqz (2 clocks) read
41 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?12 : write to read timing (example @ cl = 3, bl = 4) clk command dq dqm note: read command should be issued after t wr of ?al data input is satis?d if read command is applied to the same bank. write read d1 q1 q2 d3 masked by read t wr (min) d2 t cac (min)
42 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l reada actv nop or desl actv q1 q2 t ras (min) 2 clocks (same value as bl) t rp (min) timing diagram ?13 : read with auto-precharge (exaple @ cl = 2, bl = 2 applied to same bank) clk command dqm dq note: precharge at read with auto-precharge command (reada) is started from ?l number of clocks after the reada command is asserted. writa actv actv d1 d2 t rp (min) i rwl timing diagram ?14 : write with auto-precharge (example @ cl = 2, bl = 2 applied to same bank) clk command dqm dq note: in a case of cl = 2, precharge at write with auto-precharge command (writa) is started from ?l number of clocks after the writa command is asserted. in a case of cl = 3, precharge at write with auto-precharge command is started from ?l+1 number of clocks after the writa command. even if the ?al data is masked by dqm, the precharge does not start the clock of ?al data input. once auto-precharge command is asserted, no new command within the same bank can be issued. auto-precharge command doesn? affect at full column burst operation except burst read & single write mode. nop or desl 2 clocks (same value as bl)
43 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?15 : auto-refresh timing t rc (min) t rc (min) clk command ba ref command nop ba 1 nop nop ref nop 4 don? care notes: 1. all banks should be precharged prior to the ?st auto-refresh command (ref). 2. bank select is ignored at ref command. the refresh address and bank select are selected by internal refresh counter. 3. either nop or desl command should be asserted during t rc period while auto-refresh mode. 4. any activation command such as actv or mrs command other than ref command should be asserted after t rc from the last ref comand. 3 don? care timing diagram ?16 : self-refresh entry and exit timing t rc (min) t pde (min) clk cke command nop notes: 1. precharge command (pre or pall) should be asserted if any bank is active prior to self-refresh entry command (self). 2. self command should be asserted after the last read data have been appeared on dq. 3. the self-refresh exit command (selfx) is latched after t pde (min). it is recommended to apply nop command in conjunction with cke. 4. either nop or desl command can be used during t rc period. 5. cke should be held high within one t rc period after t pde . self don? care selfx command nop 3 nop 4 1 t si (min) 2
44 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l timing diagram ?17 : mode register set timing clk command address mrs nop or desl mode row adress actv notes: 1. the mode register set command (mrs) should only be asserted after all banks have been precharged. 2. the mrs command should only be asserted on condition that dq is in high-z. i mrd (min. 2 clocks)
45 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l n package dimensions c 1997 fujitsu limited f54003s-1c-1 54 28 1 27 "a" index 22.220.10 (.875.004) m 0.16(.006) * 20.80(.819)ref 0.80(.0315) typ 0.10(.004) 0.05(.002)min (stand off) 0.500.10 (.020.004) 10.760.20 (.424.008) 11.760.20 (.463.008) 10.160.10 (.400.004) 0.1250.05 (.005.002) details of "a" part 0.25(.010) 0.15(.006) max 0.40(.016) max 0.15(.006) lead no. 1.150.05 (.045.002) .013 ?.003 +.003 ?0.07 +0.08 0.32 (mounting height) dimensions in mm (inches) 54-lead plastic flat package (case no.: fpt-54p-m02) *: resin protrusion. (each side: 0.15 (.006) max)
46 mb81164442a-125/-100/-84/-67/-125l/-100l/-84l/-67l fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3763 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9704 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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